Mechanical planarization of a semiconductor substrate involves polishing the front surface of a wafer. The planarization is aimed at reducing the step height variations of a dielectric layer formed on the substrate's surface. Most often, the dielectric layer to be removed comprises a chemical vapor deposition (CVD) of silicon dioxide. The thickness of the step height variations lies in the range of approximately 1 micron. In most cases, the series of non-planar steps which characterize the dielectric layer have dimensions which correspond to the underlying metal lines.
According to conventional mechanical planarization techniques, the substrate is placed face down on a table covered with a pad which has been coated with an abrasive material. The silicon wafer is actually mounted to a carrier plate which is coupled to a mechanism designed to provide a downward pressure onto the substrate. Both the wafer and the table are then rotated relative to each other. The presence of the abrasive particles removes the protruding portions of the dielectric layer and physically smooths the surface of the wafer. Ideally, the goal of this type of planarization processing is to completely flatten the surface topography of the wafer.
Unfortunately, semiconductor wafers are not always entirely flat. Frequently, mechanical stresses in the crystal lattice structure produce longitudinal gradations across the wafer's surface. In effect, the surface of the silicon wafer is characterized by a gradual waviness which interferes with the uniformity of the polishing process. What happens is that some areas of the wafer end up getting overpolished, while other regions remain underpolished. To overcome the problem of non-uniform polishing, practitioners have concentrated their efforts at developing a new type of polishing pad--one that is capable of conforming to the gradual, longitudinal height variations exhibited across the semiconductor substrate surface.
At present, their efforts have resulted in a trade-off between the polishing uniformity, as measured across the wafer, and the degree of planarity achieved in more localized areas (i.e., across individual die). This trade-off reflects the fact that past approaches have either relied on very soft pads or on extremely hard ones. Soft pads generally result in good uniformity, but poor planarity, while hard pads produce good planarity, but poor uniformity.
To improve this situation, a two-layer pad has been attempted. This type of pad is made up of a hard, stiff material (in contact with the wafer) which is supported by a soft, compressible layer underneath. The object was to have the soft pad absorb most of the long range wafer height variations while the hard pad resisted bending over a moderate distance (e.g., a die spacing or less).
Unfortunately, these prior art schemes still compromise the polishing performance on two main counts. First of all, while the upper pad is intended to be stiff, it cannot be made to be too stiff, otherwise it will act as an inflexible, rigid surface, and any benefit from the underlying soft pad would be totally eliminated. Thus, the upper pad must conform or bend in such a design. Of course, this provides less than perfect planarity according to conventional methods. Realizing a pad having both good uniformity and planarity has been problematic in the past.
Secondly, while the upper pad is generally optimized for stiffness, such hardness is undesirable from the standpoint of transporting the water-based polishing medium (i.e., slurry). When slurry transport is compromised, the result is poor polishing uniformity and polishing grades. Hence, what is needed is an improved polishing pad which overcomes the above-described shortcomings.